The syn1588® Clock_M IP core offers the full syn1588® technology with a suiteable number of trigger and IO events supported. The syn1588® Clock_M IP core is suited for direct integration of a MAC and/or a processor on a single chip (SOC/SOPC design). A standard AHB interface (slave) is available for communication to the host processor executing the PTP Stack.
Typical application example is the syn1588® PCIe NIC. A standard PCIe Ethernet network interface card is made up of a single FPGA that includes the syn1588® Clock_M IP core as well as the Ethernet MAC and the PCI interface.
The syn1588® Clock_M IP core has been designed to fully maintain all real-time tasks completely within the hardware. This includes a special hardware-software interface to ensure proper communication even at high PTP packet rates. The software just implements the high level PTP data flow as defined in the IEEE1588 standard without any real-time constraints.
- fully synchronous to the system clock
- all registers of the core operate with the rising clock edge
- well commented, structured VHDL cource code
- medium footprint and medium I/O count
- advanced high-performace bus (AHB) slave interface for clock control
- media independent interface (MII or GMII) for IEEE1588 message detection
- optional user-programmable time stamper unit
- Oregano Systems‘ patented on-the-fly time-stamping
- 10/100/1000 Mbit/s Ethernet interface supported
- 10 Gbit/s Ethernet interface (XGMII) available upon request
- two event inputs, one input offers FIFO to capture dense events
- two trigger outputs, one output offers FIFO to generate dense events
- two period outputs
- one 1 pulse per second (PPS) output
- generation of interrupt upon external and internal events
- pipelined adder based clock for best synchronization results
- seperate receive and transmit timestamp FIFOs
- clock time format compatible to the IEEE1588 standard
- suited for FPGA as well as ASIC implementations
syn1588® Clock_M IP Core: Datasheet (PDF-File)
Ressources & Performance
The following table gives a rough overview of the area consumption of the
syn1588® Clock_M IP core as well as the achieved maximum frequency for selected target technologies. Note that the actual implementation figures depends on the selected target technology or FPGA device (family, package, speed grade) as well as the constraints (minimum area or maximum frequency) used for implementing the core.
Technology – Area – Frequency
- Lattice XP/lfxp20cfpbga484-3, 2866 LUTs, 2 BRAMs, 66 MHz
- Altera CycloneII/ep2c5f256c8, 3386 LEs, 4 M4K BRAMs, 73 MHz
- Altera StratixII/ep2s15f484c5, 2402 ALUTs, 4 M4K BRAMs, 83 MHz
- Xilinx Spartan3E/xc3s250e-4tq144, 2534 LUTs, 2 BRAMs, 66 MHz
- Xilinx Virtex4/xc4vlx15-10sf363, 2475 LUTs, 2 RAMB16 BRAMs, 85 MHz
Like for all Oregano Systems‘ IP cores there are two ways to license the
syn1588® Clock_M IP core.
- technology netlist license for a selected FPGA technology or device
- source code license
When ordering the technology netlist license a gate level netlist for the selected target technology is delivered. The IP core is pre-configured during the netlist generation process and cannot be changed by the user.
When ordering the source code license, the complete VHDL source code of the
syn1588® Clock_M core is delivered. Thus the customer may change the IP core as required for the application. The VHDL code is fully synthesizeable and requires no special constraints.
There is a complete verification setup for both licensing schemes available that enables system simulation and standard compliance tests.
For additional information on our syn1588® products or a detailed quotation please contact us.