No there is no license fee for using the 8051 IP Core in any project.
General Description
Oregano Systems 8051 IP Core is a 8051 compatible IP core. The design has been optimized for the requirements of a SOC design flow. Release version 1.3 of the 8051 IP core was available with September 2002. Release version 1.4 was made available in August 2004. Release version 1.6 was made available in June 2013
The 8051 IP Core had been developed in cooperation with the Vienna University of Technology. This IP core is binary compatible to the well known 8051 processor from Intel. The Oregano Systems 8051 IP core is available as a parameterizable, synthesizable circuit description (VHDL).
The Oregano Systems 8051 IP core offers faster program execution compared to the original 8051 devices due to an optimized processor’s architecture. Additionally, the Oregano Systems 8051 IP core can be parametrized. The Oregano Systems 8051 IP Core is available free of charge even for industrial applications under the LGPL (Lesser General Public License).
We kindly ask you to send us a brief feedback about your successful implementation of the Oregano Systems 8051 IP core in your FPGA or ASIC design. Please send us a brief email description or use the 8051 IP core feedback form (PDF-File).
8051 IP Core – Information
8051 Demo Designs
There are two demo designs that demonstrate how to use the 8051 IP core. These designs may easily extended to meet your project’s specific needs. Both examples are made up of a ZIP-file containing all required data (VHDL code as well as C-code) and design setup as well as documentation (PDF-File).
8051 IP on a Altera Cyclone Nios Board
This sample design uses the popular Altera Cyclone Nios evaluation board for implementing the 8051 IP core. Beside the hardware setup one can see how to compile your software and load the program code into the 8051 IP core’s program ROM.
8051 Boot Loader Demo Design
This sample design shows a simple boot loader stored in the processors on-chip ROM while the actual program is downloaded during run-time via the serial interface into the program RAM.
8051 FAQ
This is the FAQ – Frequently Asked Questions – of Oregano Systems‘ 8051 IP Core. We received a lot of feedback and questions from users all over the world. In order to simply using our free 8051 IP Core we decided to summarize the most frequently heard questions – as well as their answers, of course.
We kindly ask you first to browse through this FAQ list prior contacting our support staff via e-mail.
You will find the most recent version of the public available 8051 IP Core always at our web site.
The target FPGA family shall offer sufficient amount of on-chip memory blocks to embed at least all RAMs you connect to the 8051 IP core on-chip. The ROM is very often still implemented externally in a Flash device. Generally spoken it will speed up your design if you keep all memories on chip.
Beside memory blocks one needs sufficient logic resource to implement the 8051 IP core as well as other logic. Usually it does not make sense just to implement a processor in a FPGA. The resources required depend on your parameters you have choosen for the 8051 IP core. For a fist estimate just calculate approx. 3500 LUTs.
You are trying to synthesize our sample simulation models of the memories. This leads of course to these errors. Memories are technology specific and are usually generated by special generator software like Altera’s Megafunction Wizard or Xilinx‘ Core Generator.
We strongly encourage to use dedicated FPGA synthesis tools like Mentor’s Leonardo and Precision or Synplicity’s Synplify. For ASIC designs we recommend to use Synopsys‘ DesignCompiler. Generlally the VHDL code of the 8051 IP core is tool independent. I.e. any standard synthesis tool shall be capable to synthesize the VHDL code to your selected target technology.
The FPGA vendor’s synthesis tools (note: not the OEM versions of dedicated synthesis tools but tools developed by FPGA vendors!) are frequently somewhat limited in their functionality compared to dedicated synthesis tools. They often do not support all VHDL constructs or end up larger but slower circuits. There are often requirements that entity and architecture have to be in the same file etc. We generally recommend to use dedicated synthesis tools for synthesizing circuits.
The difference is mainly the procesor’s basic architecture. The 8051 processor is a CISC processor while the FPGA vendor’s configurable processors are RISC processors. Additionally these processors have been optimized to be implemented efficiently on their specific target technology.
We recommend to use the 8051 processor whenever the already existing software written for that processor has to be reused. For these projects one may benefit from the SOC integration using our 8051 IP core. For completely new products where also the software development starts from scratch we recommend to use another processor architecture.
You have sent a question to our contact mail adress and did not received an answer? There may be several reasons for this. We offer this service free of charge. Thus it may take some days until we are able to answer your questions because we are busy with our commercial projects. Usually you will receive the answer within two days. Frequently, emails to the 8051 support address are infected with some kind of viruses. On the average about one quarter of the emails we receive are infected. Our virus scan deletes all this messages automatically without further notice.
8051 IP Core – Features & Downloads
Features
- fully synchronous circuit design
- single clock
- synthesizable circuit description
- OP code compatible to original Intel 8051 device
- faster command execution due to a new architecture
- all commands are executed in 1-4 clock cycles depending on the number of operands
- separate RAM and ROM data/address bus
- parameterizable number of timer and UART units
- conventional multiplying algorithm or fast parallel multiplier units
- conventional dividing algorithm or fast parallel divider units
- verified to be compatible using extensive simulations – but no guarantee
Downloads
Datasheet
User Guide
Licensing
Source Files
User Comments
- Dr. Aleksander H. Mursaev, professor at the Saint Petersburg Electrotechnical University Department of Computer Science & Engineering said:
„… it is highly useful for my didactical work because it looks to be an excellent illustrative material.“
- Felix Bauer, from OFFIS about the mc8051 IP core:
„Thanks a lot for the mc8051 source code. It is well structured and therefore easy to understand. We have mapped the core onto a Virtex FPGA, and it works without any complications.“
8051 IP Core – List of Corrected Bugs
- CJNE: When execute the instrument of (CJNE @Ri, #data, rel),
if @Ri >= data the carry must be cleared. In the 8051 IP core revision 1.5 the carry(PSW.7) had not been cleared. - RETI: Stackpointer had been corrupted when executing a certain sequence of RETI and RET commands.
- SIU: Stop bits had been erroneously interpreted in certain modes and conditions.
- Baud generation for the serial interface using 0xFF as reload value did not work. This has been corrected.
- Interrupt during some instructions led the stack pointer be set incorrectly. This has been corrected.
- After a RETI there is erroneously not one instruction executed before going to a pending interrupt. When an interrupt is pending and the instruction executed is RETI or a write access to IE or IP one more instruction is executed before vectoring to the interrupt routine. This has been corrected.
- Interrupt service routine erroneously executed twice for a level activated interrupt. This has been corrected.
- The synchronization stage of the interrupt inputs in the timer/counter unit has been hardened with additional series flip-flops due to the high operating frequencies nowadays in use.
- A pre-scaler in the serial interface unit has been changed to 1/12 instead of 1/16 to conform to mode 0 data book descriptions.
- The carry flag was incorrectly reset during a special situation. This has been corrected.
- tmr/ctr1 erroneously used his run flag although tmr/ctr0 was in mode 3. This has been corrected.
- Corrected behavior of RETI instruction handling
- Added synchronization for interrupt signals
- Corrected timer problems.
- Added more complex synthesis setup for Synplicity’s SynplifyPro FPGA synthesis tool for various FPGA families.
- Added demo designs for implementing the 8051 IP core onto Altera’s Cyclone Nios evaluation board.
- The misbehavior during duplex operation in file mc8051_siu_rtl.vhd, revision 1.7 and below has been corrected with revision 1.8 of this file.
- Some XCH instructions did not work properly when using the internal RAM block in file control_mem_rtl.vhd, revision 1.7 and below and in file control_fsm_rtl.vhd, revision 1.6 and below. This problem has been corrected with revision 1.8 of file control_mem_rtl.vhd and with revision 1.7 of file control_fsm_rtl.vhd.
- The boolean instructions ANL and ORL delivered wrong results under certain conditions in file control_mem_rtl.vhd, revision 1.7 and below. This misbehavior has been corrected with revision 1.8 of this file.
- The problem with the POP SP command in file control_mem_rtl.vhd, revision 1.7 and below has been corrected with revision 1.8 of this file.
- The misbehavior with clearing the IEx-flags in file control_fsm_rtl.vhd, revision 1.6 and below has been corrected with revision 1.7 of this file.
- Register TMOD had high and low nibble swapped in file mc8051_tmrctr_rtl.vhd, revision 1.6 and below. This error has been corrected with revision 1.7.
- Register SCON had Bits SM0 and SM1 swapped in file mc8051_siu_rtl.vhd, revision 1.6 and below. This error has been corrected with revision 1.7.
- In mode 0 the serial interface unit did not output a clock signal when shifting in the eighth data bit in file mc8051_siu_rtl.vhd, revision 1.6 and below. This error has been corrected with revision 1.7.
If you have any comments or questions regards our 8051 IP core please feel free to contact us. We also offer – commercial – support for using and/or adapting the 8051 IP core in your industrial FPGA/ASIC designs. Please contact us for more details!
Contact Support
Contact us
contact@oregano.at
PHONE
+43 676 84 31 04 -200
+43 676 84 31 04 -300
ADDRESS
Franzosengraben 8
1030 Vienna