General Description


Oregano Systems 8051 IP Core is a 8051 compatible IP core. The design has been optimized for the requirements of a SOC design flow. Release version 1.3 of the 8051 IP core was available with September 2002. Release version 1.4 was made available in August 2004. Release version 1.6 was made available in June 2013

The 8051 IP Core had been developed in cooperation with the Vienna University of Technology. This IP core is binary compatible to the well known 8051 processor from Intel. The Oregano Systems 8051 IP core is available as a parameterizable, synthesizable circuit description (VHDL).


The Oregano Systems 8051 IP core offers faster program execution compared to the original 8051 devices due to an optimized processor’s architecture. Additionally, the Oregano Systems 8051 IP core can be  parametrized. The Oregano Systems 8051 IP Core is available free of charge even for industrial applications under the LGPL (Lesser General Public License).


We kindly ask you to send us a brief feedback about your successful implementation of the Oregano Systems 8051 IP core in your FPGA or ASIC design. Please send us a brief email description or use the 8051 IP core feedback form (PDF-File).

8051 IP Core – Information

8051 Demo Designs

There are two demo designs that demonstrate how to use the 8051 IP core. These designs may easily extended to meet your project’s specific needs. Both examples are made up of a ZIP-file containing all required data (VHDL code as well as C-code) and design setup as well as documentation (PDF-File).


8051 IP on a Altera Cyclone Nios Board

This sample design uses the popular Altera Cyclone Nios evaluation board for implementing the 8051 IP core. Beside the hardware setup one can see how to compile your software and load the program code into the 8051 IP core’s program ROM.


8051 Boot Loader Demo Design

This sample design shows a simple boot loader stored in the processors on-chip ROM while the actual program is downloaded during run-time via the serial interface into the program RAM.




8051 FAQ

This is the FAQ – Frequently Asked Questions – of Oregano Systems‘ 8051 IP Core. We received a lot of feedback and questions from users all over the world. In order to simply using our free 8051 IP Core we decided to summarize the most frequently heard questions – as well as their answers, of course.


We kindly ask you first to browse through this FAQ list prior contacting our support staff via e-mail.


8051 IP Core – Features & Downloads


  • fully synchronous circuit design
  • single clock
  • synthesizable circuit description
  • OP code compatible to original Intel 8051 device
  • faster command execution due to a new architecture
  • all commands are executed in 1-4 clock cycles depending on the number of operands
  • separate RAM and ROM data/address bus
  • parameterizable number of timer and UART units
  • conventional multiplying algorithm or fast parallel multiplier units
  • conventional dividing algorithm or fast parallel divider units
  • verified to be compatible using extensive simulations – but no guarantee


User Comments

  • Dr. Aleksander H. Mursaev, professor at the Saint Petersburg Electrotechnical University Department of Computer Science & Engineering said:
    „… it is highly useful for my didactical work because it looks to be an excellent illustrative material.“
  • Felix Bauer, from OFFIS about the mc8051 IP core:
    „Thanks a lot for the mc8051 source code. It is well structured and therefore easy to understand. We have mapped the core onto a Virtex FPGA, and it works without any complications.“

8051 IP Core – List of Corrected Bugs

!  8051 IP Core– Ordering & Support

If you have any comments or questions regards our 8051 IP core please feel free to contact us. We also offer – commercial – support for using and/or adapting the 8051 IP core in your industrial FPGA/ASIC designs. Please contact us for more details!

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