Mrz 012017
New: Revision 2.1 of the syn1588<sup>®</sup> PCIe NIC available!

This week, the brand new revision 2.1 of our syn1588® PCIe NIC arrived! Beside the well known high-performance, high-accuracy features we added the new exciting functions. It is now optionally possible to drive the syn1588® hardware clock with an external clock signal. For all users that require internal connectivity we improved our internal SMA connectors. Starting with this board revision one will observe a new IEEE OUI for the Ethernet address. Please check the full data sheet or the brief data sheet of the syn1588® PCIe NIC for more details. Please also observe the new „ordering a syn1588® PCIe NIC“ [more…]

Jan 192017
Hiring: Software Engineer m/f

You are looking for a new opportunity? You are a self-motivated software engineer with excellent C/C++ skills? You are a team player and ideally used to write embedded software? You would like to join the world leading clock synchronisation experts? Oregano Systems is expanding its software team to increase our work force. We are offering a permanent full-time employment in our highly motivated team. English fluent in spoken and written is required, German is welcomed but not required. A valid working permit for non Austrian citizen is mandatory. We do not expect miracles but spirit and dedication. We at Oregano [more…]

Dez 152016
Advance Information: syn1588<sup>®</sup> VIP Eval Board - Revision 3

In Q3/2017 the new Revision 3 of Oregano Systems‘ single chip IEEE1588 solution the syn1588® VIP evaluation board will be available. The design has been updated to meet the latest customer requirements. The syn1588® VIP evaluation board Revision 3 will be USB powered. We added the video sync generation capability as well as the jitter cleaner PLL for arbitrary high-speed clock generation. The UART output will also be available via USB further simplifying the usage of the evaluation board. A GPS receiver will be available on-board as well. The Ethernet network interface can be chosen either to use standard copper [more…]

Nov 292016
PCB Design Show Case: High Speed Camera

Designing an ultra fast camera with integrated image processing requires dense packaging of both sensitive analog electronics as well as high speed digital processing power and communication. The solution: The PCBs are typically rigid-flex boards folded into the camera case. AIT’s (Austrian Institute of Technology) latest high-speed camera development, the xposure camera, offers impressive features 60×2016 pixels 600kHz line rate 40 Gbit Ethernet interface in-system hardware based image pre-processing small size 85 x 85 x 85 mm Packing all these features into such a small volume created a huge challenge for the PCB design. Read the full article that briefly [more…]

Okt 282016

Today Mr. Kirvy Teo co-founder and vicepresident of Plunify Pte Ltd visited Oregano Systems. Plunify designed a new high performance FPGA optimization tool InTime. InTime runs on top of the FPGA backend tools and automatically optimizes parameters, seeds etc. in order to meet the design goals: timing area power Mr. Teo visited Austria as part of the GIN Go-Austria initiative (Global Incubator Network). Oregano Systems had been chosen for the visit due to our FPGA expertise. Oregano Systems uses FPGAs in all complexity levels since their very beginnings. Plunify and Oregano Systems agreed on a schedule to prove the capabilities [more…]

Okt 242016
New: The syn1588<sup>®</sup> NIC Box

Today Oregano Systems announced the new syn1588® NIC Box; another member of the syn1588® product family. The syn1588® NIC Box further eases the process of setting up high accuracy clock synchroniation systems. A ready-to-use clock synchronization solution without any install operation; just plug-in the device into your network. The syn1588® NIC Box is a highly versatile, high performance PTP node capable of delivering a variety of precise timing signals. Aside from a standard 1 pulse per second, two arbitrary frequencies as well as an IRIG-B signal can be generated. It is designed to receive or transmit timing information over an [more…]