19 Aug 2015
Generating low-jitter clocks

The Oregano Systems’ syn1588® PCIe NIC Revision 2allows the generation of low-jitter clock signals. The syn1588® PCIe NIC Revision 2 is equipped with an external jitter-cleaner PLL that removes the jitter of the digitally generated, synchronized clocks. Furthermore it allows generation of high frequency single-ended clock signals (up to 150 MHz). The generated clock signals can be routed to any of the onboard SMA connectors.


There are two utilities that allow the user to simply specify the required output frequencies. There is an application note (PDF file) available describing all the details of how to set the output frequencies as well as the pre-requisites.

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