syn1588® VIP IP Core

The syn1588^® VIP is a highly integrated single-chip IEEE1588 solution. Just connect the syn1588^® VIP to the Ethernet and receive highly accurate synchronized time or frequency.

The syn1588^® VIP IP core enables the integration of a full IEEE1588 solution into your SOC design. It includes all required hardware and software functions. The syn1588^® VIP may be integrated into both FPGA or ASIC designs. With its unrivaled small memory footprint of approx. 512 Kbytes of ROM and approx. 128k Kbytes of RAM Oregano Systems‘ syn1588^® VIP IP core is at the leading edge of easy to use, small, technology independent, and yet fully compatible clock synchronization solutions.

The syn1588^® VIP IP core is fully configurable to allow support of different network modes (Layer 2, IPv4, IPv6), different PTP profiles and network link speeds. Recently, we even added 25 Gbit support for the syn1588^® VIP IP core. Parameters may be stored in an external non-volatile memory to allow the user to change and save the default PTP parameters. For the CPU either a softcore processor (typically a 32 bit RISC type CPU) is used or alternatively, the hardcore processor available in today's SoC FPGAs.

We offer a syn1588^® VIP evaluation board allowing customers to test drive the syn1588^® VIP IP core without any risk.