The syn1588® Clock_M IP core offers the full syn1588® technology with a suitable number of trigger and IO events supported. The syn1588® Clock_M IP core is suited for direct integration of a MAC and/or a processor on a single chip (SoC/SoPC design). A standard AXI4 Lite interface (slave) is available for communication to the host processor executing the PTP Stack.


A typical application example is the syn1588® PCIe NIC. A standard PCIe Ethernet network interface card is made up of a single FPGA that includes the syn1588® Clock_M IP core as well as the Ethernet MAC and the PCIe interface



syn1588® Clock_M – Information

The following figure shows a typical application scenario: The syn1588® Clock_M IP core is accompanied by an Ethernet MAC, an (eventually external) Ethernet PHY and a CPU.



The syn1588® Clock_M IP core has been designed to fully maintain all real-time tasks completely within the hardware. This includes a special hardware-software interface to ensure proper communication even at high PTP packet rates. The software just implements the high level PTP data flow as defined in the IEEE1588 standard without any real-time constraints.

syn1588® Clock_M – Features

  • fully synchronous to the system clock
  • all registers of the core operate with the rising clock edge
  • well commented, structured VHDL source code
  • medium footprint and medium I/O count
  • AXI4 Lite type slave interface for clock control using independent CPU clock domain
  • 25/X/G/MII netwook interface for IEEE1588 message detection (packet timestamping)
  • optional user-programmable time stamper unit
  • Oregano Systems‘ patented on-the-fly time-stamping (1-step operation)
  • 100/1000 Mbit/s link speed support
  • 10 Gbit/s link speed support
  • New! 25 Gbit/s link speed support
  • two timestamp input signals (EVENT function). One EVENT input offers FIFO to capture dense events. This can be used to synchronize to an external GPS-based time source via a 1 PPS signal. Minimum pulse width is 3 x syn1588® clock period.
  • Generation of two a-periodic, one-time events (TRIGGER function). One TRIGGER output offers FIFO to generate dense events. TRIGGERs may be used to start the PERIOD function to allow a precise absolute phase definition in the whole PTP network
  • two PERIOD outputs allowing generation of periodical signals (clocks) in a frequency range from mHZ to MHz with a resolution of 2-45 ns
  • one 1 pulse per second (PPS) output
  • generation of digital IRIG-B output stream (DCLS mode IRIG-B000)
  • decoding of digital IRIG-B input stream (DCLS mode IRIG-B000)
  • generation of interrupts upon external and internal events
  • pipelined adder based clock for best synchronization results
  • separate receive and transmit timestamp FIFOs
  • clock time format compatible to the IEEE1588 standard
  • suited for FPGA as well as ASIC implementations
  • optional SMPTE 2059 compatible signal generation


syn1588® Clock_M – Resources & Licenses

Resources & Performance

The following table gives a rough overview of the area consumption of the syn1588® Clock_M IP core as well as the achieved maximum frequency for selected target technologies. Note that the actual implementation figures depends on the selected target technology or FPGA device (family, package, speed grade) as well as the constraints (minimum area or maximum frequency) used for implementing the core.


Resource Utilization

The following table shows the design resources for the syn1588® Clock_M IP core with a single 100/1000 Mbit network interface. All features have been turned on.


  • Altera/Intel Arria 10/10AS066K1F40E1SG, 5531 ALM, 6 M20K
  • Altera/Intel Cyclone V/5CEBA9F31C8, 2402 ALUTs, 5519 ALM, 6 M20K
  • Xilinx Kintex7/XCKU040-FFVA1156-2-E, 7069 LUTs, 9 RAMB36, 1 RAMB18


Like for all Oregano Systems‘ IP Cores, there are two ways to license the syn1588® Clock_M IP core.


  • technology netlist license for a selected FPGA technology or device
  • source code license

When ordering the technology netlist license a gate level netlist for the selected target technology is delivered. The IP core is pre-configured during the netlist generation process and cannot be changed by the user.


When ordering the source code license, the complete VHDL source code of the syn1588® Clock_M core is delivered. Thus the customer may change the IP core as required for the application. The VHDL code is fully synthesizable and requires no special constraints.

!  syn1588® Clock_M– Ordering & Support

More Information

For additional information on our syn1588® products or a detailed quotation please contact us.

Contact Support

This could also be of interest

Contact us



+43 676 84 31 04 -200
+43 676 84 31 04 -300


Franzosengraben 8
1030 Vienna