The 8051 IP Core was developed in cooperation with the Vienna University of Technology. This processor core is binary compatible to the well known 8051 processor from Intel. The Oregano Systems 8051 IP core is available as a parameterizeable, synthesizeable circuit description (VHDL).
The Oregano Systems 8051 IP core offers faster program execution compared to the original 8051 devices since we have optimized the processor’s architecture. Additionally the 8051 IP core offers some sort of parametrize ability. The Oregano Systems 8051 IP Core is available free of charge even for industrial applications under the LGPL (Lesser General Public License).
We kindly ask you to send us a brief feedback about your successfully implementation of the Oregano Systems 8051 IP core in your FPGA or ASIC design. Please send us a brief email description or use the 8051 IP core feedback form(PDF-File).
Frequently Asked Questions
8051 IP Core FAQ
8051 Demo Designs
This is a 8051 compatible IP core. The design has been optimized for the requirements of a SOC design flow. Release version 1.3 of the 8051 IP core was available with September 2002. Release version 1.4 was made available in August 2004. Release version 1.6 was made available in June 2013
- fully synchronous circuit design
- single clock
- synthesizeable circuit description
- OP code compatible to original Intel 8051 device
- faster command execution due to new architecture
- all commands are executed in 1-4 clock cycles depending on the number of operands
- separate RAM and ROM data/address bus
- parametrizeable number of timer and UART units
- conventional multiplying algorithm or fast parallel multiplier units
- conventional dividing algorithm or fast parallel divider units
- verified to be compatible using extensive simulations – but no guarantee
Brief product description (PDF-File)
MC8051 IP Core User Guide (PDF-File)
GNU LESSER GENERAL PUBLIC LICENSE (PDF-File)
8051 IP Core (PDF-File)
The VHDL source files of the IP core are provided in a single zip-file (223 kb). The VHDL files naturally include a complete testbench that enables the user to verify the function of the MC8051 IP core and the software written. Beside the VHDL files we provide synthesis scripts for popular FPGA synthesis tools and a very simple script for ASIC synthesis using Synopsys’s DesignCompiler. Please note that there are two different kinds of version identifiers used in the MC8051 project. There is the release version ID that denotes the version of the whole distribution (i.e. the zip-file). And there are the version identifiers used for every single design file generally referred to as the revision in the list of known bugs.
- Dr. Aleksander H. Mursaev, professor at the Saint Petersburg Electrotechnical University Department of Computer Science & Engineering said:
“… it is highly useful for my didactical work because it looks to be an excellent illustrative material.”
- Felix Bauer, from OFFIS about the mc8051 IP core:
“Thanks a lot for the mc8051 source code. It is well structured and therefore easy to understand. We have mapped the core onto a Virtex FPGA, and it works without any complications.”
Although we have set huge efforts to verify the proper operation and compatibility of the 8051 IP core we accept that there still might be some bugs. We will provide you in the following a list of known bugs, work around and bug fixes. We encourage you to send us a detailed bug report if you find a misbehavior of the 8051 IP core.
List of Corrected Bugs
Changes with release version 1.6
- CJNE: When execute the instrument of (CJNE @Ri, #data, rel),
if @Ri >= data the carry must be cleared. In the 8051 IP core revision 1.5 the carry(PSW.7) had not been cleared.
- RETI: Stackpointer had been corrupted when executing a certain sequence of RETI and RET commands.
- SIU: Stop bits had been erroneously interpreted in certain modes and conditions.
Changes with release version 1.5
- Baud generation for the serial interface using 0xFF as reload value did not work. This has been corrected.
- Interrupt during some instructions led the stack pointer be set incorrectly. This has been corrected.
- After a RETI there is erroneously not one instruction executed before going to a pending interrupt. When an interrupt is pending and the instruction executed is RETI or a write access to IE or IP one more instruction is executed before vectoring to the interrupt routine. This has been corrected.
- Interrupt service routine erroneously executed twice for a level activated interrupt. This has been corrected.
- The synchronization stage of the interrupt inputs in the timer/counter unit has been hardened with additional series flip-flops due to the high operating frequencies nowadays in use.
- A pre-scaler in the serial interface unit has been changed to 1/12 instead of 1/16 to conform to mode 0 data book descriptions.
- The carry flag was incorrectly reset during a special situation. This has been corrected.
- tmr/ctr1 erroneously used his run flag although tmr/ctr0 was in mode 3. This has been corrected.
Changes with release version 1.4
- Corrected behavior of RETI instruction handling
- Added synchronization for interrupt signals
- Corrected timer problems.
- Added more complex synthesis setup for Synplicity’s SynplifyPro FPGA synthesis tool for various FPGA families.
- Added demo designs for implementing the 8051 IP core onto Altera’s Cyclone Nios evaluation board.
Changes with release version 1.3
- The misbehavior during duplex operation in file mc8051_siu_rtl.vhd, revision 1.7 and below has been corrected with revision 1.8 of this file.
Changes with release version 1.2
- Some XCH instructions did not work properly when using the internal RAM block in file control_mem_rtl.vhd, revision 1.7 and below and in file control_fsm_rtl.vhd, revision 1.6 and below. This problem has been corrected with revision 1.8 of file control_mem_rtl.vhd and with revision 1.7 of file control_fsm_rtl.vhd.
- The boolean instructions ANL and ORL delivered wrong results under certain conditions in file control_mem_rtl.vhd, revision 1.7 and below. This misbehavior has been corrected with revision 1.8 of this file.
- The problem with the POP SP command in file control_mem_rtl.vhd, revision 1.7 and below has been corrected with revision 1.8 of this file.
- The misbehavior with clearing the IEx-flags in file control_fsm_rtl.vhd, revision 1.6 and below has been corrected with revision 1.7 of this file.
Changes with release version 1.1
- Register TMOD had high and low nibble swapped in file mc8051_tmrctr_rtl.vhd, revision 1.6 and below. This error has been corrected with revision 1.7.
- Register SCON had Bits SM0 and SM1 swapped in file mc8051_siu_rtl.vhd, revision 1.6 and below. This error has been corrected with revision 1.7.
- In mode 0 the serial interface unit did not output a clock signal when shifting in the eighth data bit in file mc8051_siu_rtl.vhd, revision 1.6 and below. This error has been corrected with revision 1.7.
Contact and Support
If you have any comments or questions regards our 8051 IP core please feel free to contact us. We also offer – commercial – support for using and/or adapting the 8051 IP core in your industrial FPGA/ASIC designs. Please contact us for more details!