syn1588® Clock_S


The syn1588® Clock_S IP core offers the full syn1588® technology with a minimum amount of ressources required. There are only a minimum of trigger and IO events supported. A small synchronous serial interface is used for communication to the host processor executing the PTP Stack.

Typical application is to enable an existing microcontroller by the IEEE1588 functions for cost sensitive high volume designs. The syn1588® Clock_S IP core is implemented in a small FPGA that is located between the MAC of the microcontroller and the external PHY. The MII bus has to be fed through the FPGA. Additionally a control path to the processor is established using the SPI interface.


  • fully synchronous to the system clock
  • all registers of the core operate with the rising clock edge
  • well commented, well structured VHDL cource code
  • small footprint and small I/O count
  • serial peripheral interface (SPI) for clock control
  • media independent interface (MII) for sync message detection
  • one event input, one trigger output, one period output, one 1 pulse per second (PPS) output
  • pipelined adder based clock for best synchronization results
  • seperate receive and transmit timestamp FIFOs
  • clock time format compatible to the IEEE1588 standard
  • suited for FPGA as well as ASIC implementations

Data Sheet
syn1588® Clock_S IP Core: Datasheet (PDF-File)

Ressources & Performance
The following table gives a rough overview of the area consumption of the
syn1588® Clock_S IP core as well as the achieved maximum frequency for selected target technologies.
Note that the actual implementation figures depends on the selected target technology or FPGA device (family, package, speed grade) as well as the constraints (minimum area or maximum frequency) used for implementing the core.

Technology – Area – Frequency

  • Lattice XP/lfxp20cfpbga484-3,  2160 LUTs, 2 BRAMs, 70 MHz
  • Altera CycloneII/ep2c5f256c8, 1996 LEs, 4 M4K BRAMs, 60 MHz
  • Altera StratixII/ep2s15f484c5, 1925 ALUTs, 4 M4K BRAMs, 90 MHz
  • Xilinx Spartan3E/xc3s250e-4tq144, 1724 LUTs, 2 BRAMs, 77 MHz
  • Xilinx Virtex4/xc4vlx15-10sf363, 1698 LUTs, 2 RAMB16 BRAMs, 100 MHz

Like for all Oregano Systems‘ IP cores there are two ways to license the
syn1588® Clock_S IP core.

  • technology netlist license for a selected FPGA technology or device
  • source code license

When ordering the technology netlist license a gate level netlist for the selected target technology is delivered. The IP core is pre-configured during the netlist generation process and cannot be changed by the user.

When ordering the source code license, the complete VHDL source code of the
syn1588® Clock_S core is delivered. Thus the customer may change the IP core as required for the application. The VHDL code is fully synthesizeable and requires no special constraints.

There is a complete verification setup for both licensing schemes available that enables system simulation and standard compliance tests.

More Information
For additional information on our syn1588® products or a detailed quotation please contact us.